Sample Midterm Test

PwnHero ELE 818 * ADVANCED COMPUTER ARCHITECTURES * MIDTERM TEST * SAMPLE 1 Section: Simple pipeline for integer operations For all following questions we assume that: a) Pipeline contains 5 stages: IF, ID, EX, M and W; b) Each stage requires one clock cycle; c) All memory references hit in cache; d) Following program segment should be processed: // ADD TWO INTEGER ARRAYS LW R4 # 400 L1: LW R1, 0 (R4) ; Load first operand LW R2, 400 (R4) ; Load second operand ADDI R3, R1, R2 ; Add operands SW R3, 0 (R4) ; Store result SUB R4, R4, #4 ; Calculate address of next element BNEZ R4, L1 ; Loop if (R4) != 0 Question # 1.1 Calculate how many clock cycles will take execution of this segment on the regular (non- pipelined) architecture. Show calculations: Number of cycles = (2) Question # 1.2 Calculate how many clock cycles will take execution of this segment on the simple pipeline without forwarding or bypassing when result of branch instruction (new PC content) is available after WB stage. Show timing of one loop turn on Fig 1.1: Instruction Clock cycle number . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 LW R1, 0 (R4) LW R2, 400 (R4) ADDI R3,R1,R2 SW R3, 0 (R4) SUB R4, R4, #4 BNEZ R4, L1 Fig 1.1 Number of cycles = (2) PwnHero.com